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Metrology for manufacturing 3D stacked integrated circuits

Short Name: 3D Stack, Project Number: 14IND07
Image showing a Circuit board
Circuit board

Helping industry to increase the functionality of 3D chips

Building on the Digital Agenda for Europe the Digital Europe programme aims to develop the strategic digital capacities of the EU and facilitate the wide deployment of these technologies. In support of this ‘3D’ chips and 3D semiconductor technologies have been identified by the European Electronic Leaders Group as the key opportunity for growth in Europe. This technology uses copper ‘Through Silicon Vias’ (TSVs) to electrically connect stacks of semiconductor wafers and dies to produce what are known as ‘3D stacked integrated circuits‘. Unlike 2D chips TSVs have a much larger density of high aspect-ratio (HAR) components. These are tall but have a small surface area and often feature sharp edges which were hard to detect accurately using light microscopes. For this technology to progress manufacturers needed new, accurate and traceable methodologies to address the measurement issues created by HAR TSVs due to their 3D architecture, nanoscale dimensions and the heat caused by the higher current densities.

This project created various types of TSV structures along with a suite of methods and instrumentation for characterising them. For non-destructive measurements on sample surface features a novel 3D Atomic Force Microscope was developed capable of scan speeds up to 1 mm/s, a 50-fold increase on existing instruments.

Information on TSV grain size, orientation, grain boundary properties and dimensional data were obtained through a combination of SEM and light microscopy measurements.

To measure voids and contaminants X-ray and μX-ray fluorescence (XRF) measurements were performed on TSV cross sections and relevant atomic fundamental parameters were determined and validated for reference-free XRF.

To inform on the performance of 3D microscopes in detecting nanometer sized structures such as HARs a new calibration standard was developed.

A ‘lock-in thermography’ set- up, was created to accurately measure the electrical and temperature changes of nanostructured copper TSV interconnects and used to identify hot spots in new electronic devices in collaboration with an industrial partner.

A wide range of other techniques were explored to characterise TSVs including confocal microscopy, Raman spectroscopy, GHz-SAM, optical and i/r interferometry.


Most of the techniques, procedures and methodologies developed have been validated for accuracy and traceability, some of which have been incorporated into four guides for TSV characterisation which are available for download from the project’s webpage.


As a result of the project new calibration services a metrological infra-structure is now available for TSV based 3D integrated circuits which will play an important role in the introduction of this technology, ensuring a competitive advantage for Europe in this field.


Project website
Other Participants
Commissariat à l'énergie atomique et aux énergies alternatives (France)
Fogale nanotech (France)
Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V. (Germany)
Interuniversitair Micro-Electronica centrum (Belgium)


2015 - 2018